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ISL6520A
Data Sheet March 28, 2007 FN9016.5
Single Synchronous Buck Pulse-Width Modulation (PWM) Controller
The ISL6520A makes simple work out of implementing a complete control and protection scheme for a DC/DC stepdown converter. Designed to drive N-Channel MOSFETs in a synchronous buck topology, the ISL6520A integrates the control, output adjustment, monitoring and protection functions into a single 8-Lead package. The ISL6520A provides simple, single feedback loop, voltage-mode control with fast transient response. The output voltage can be precisely regulated to as low as 0.8V, with a maximum tolerance of 1.5% over-temperature and line voltage variations. A fixed frequency oscillator reduces design complexity, while balancing typical application cost and efficiency. The error amplifier features a 15MHz gain-bandwidth product and 8V/ms slew rate which enables high converter bandwidth for fast transient performance. The resulting PWM duty cycles range from 0% to 100%. Protection from overcurrent conditions is provided by monitoring the rDS(ON) of the upper MOSFET to inhibit PWM operation appropriately. This approach simplifies the implementation and improves efficiency by eliminating the need for a current sense resistor.
Features
* Operates from +5V Input * 0.8V to VIN Output Range - 0.8V Internal Reference - 1.5% Over Line Voltage and Temperature * Drives N-Channel MOSFETs * Simple Single-Loop Control Design - Voltage-Mode PWM Control * Fast Transient Response - High-Bandwidth Error Amplifier - Full 0% to 100% Duty Cycle * Lossless, Programmable Overcurrent Protection - Uses Upper MOSFET's rDS(ON) * Small Converter Size - 300kHz Fixed Frequency Oscillator - Internal Soft-Start - 8 Ld SOIC or 16 Ld 4mmx4mm QFN * QFN Package: - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline - Near Chip Scale Package footprint, which improves PCB efficiency and has a thinner profile * Pb-Free Plus Anneal Available (RoHS Compliant)
Pinouts
ISL6520A (6 LD SOIC) TOP VIEW
BOOT 1 UGATE 2 GND 3 LGATE 4 8 PHASE 7 COMP/SD 6 FB 5 VCC
Applications
* Power Supplies for Microprocessors - PCs - Embedded Controllers * Subsystem Power Supplies - PCI/AGP/GTL+ Buses - ACPI Power Control - SSTL-2 and DDR SDRAM Bus Termination Supply * Cable Modems, Set Top Boxes, and DSL Modems * DSP and Core Communications Processor Supplies
NC
ISL6520A (16 LD QFN) TOP VIEW
PHASE NC NC
* Memory Supplies * Personal Computer Peripherals
12 NC 11 COMP/OCSET 10 NC
16 BOOT UGATE GND NC 1 2 3 4 5 LGATE
15
14
13
* Industrial Power Supplies * 5V-Input DC/DC Regulators * Low-Voltage Distributed Power Supplies
9 6 NC 7 VCC 8 NC
FB
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004, 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6520A Ordering Information
PART NUMBER ISL6520ACB* ISL6520ACBZ* (Note) ISL6520ACBZA* (Note) ISL6520AIB* ISL6520AIBZ* (Note) ISL6520ACR* ISL6520ACRZ* (Note) ISL6520AIR* ISL6520AIRZ * (Note) ISL6520EVAL1 PART MARKING 6520 ACB 6520 ACBZ 6520 ACBZ 6520 AIB 6520 AIBZ 65 20ACR 65 20ACRZ 65 20AIR 65 20AIRZ Evaluation Board TEMP. RANGE (C) 0 to +70 0 to +70 0 to +70 -40 to +85 -40 to +85 0 to +70 0 to +70 -40 to +85 -40 to +85
PACKAGE 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 16 Ld 4x4mm QFN 16 Ld 4x4mm QFN (Pb-free) 16 Ld 4x4mm QFN 16 Ld 4x4mm QFN (Pb-free) M8.15 M8.15 M8.15 M8.15 M8.15
PKG. DWG. #
L16.4x4 L16.4x4 L16.4x4 L16.4x4
*Add "-T" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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FN9016.5 March 28, 2007
ISL6520A Block Diagram
VCC
SAMPLE AND HOLD
OC COMPARATOR
+ -
POR AND SOFTSTART
BOOT UGATE
PHASE + 0.8V FB COMP/OCSET 20A OSCILLATOR FIXED 300kHz GND LGATE ERROR AMP + PWM COMPARATOR + INHIBIT
GATE CONTROL PWM LOGIC
VCC
Typical Application
VCC
CDCPL VCC ROCSET 5
CBULK DBOOT 1 BOOT CBOOT LOUT
CHF
COMP/OCSET 7 RF CI CF FB ROFFSET 6 3 GND ISL6520A
2 8 4
UGATE PHASE LGATE
+VO
COUT
RS
3
FN9016.5 March 28, 2007
ISL6520A
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V Absolute Boot Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . +15.0V Upper Driver Supply Voltage, VBOOT - VPHASE . . . . . . . . 7.0V (DC) 8.0V (<10ns Pulse Width, 10J) Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance JA (C/W) JC (C/W) SOIC Package (Note 1) . . . . . . . . . . . . . . 95 N/A QFN Package (Notes 2, 3). . . . . . . . . . . . . 45 7 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . -65C to +150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300C (SOIC - Lead Tips Only)
Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 10% Ambient Temperature Range - ISL6520AC . . . . . . . . . 0C to +70C Ambient Temperature Range - ISL6520AI . . . . . . . . .-40C to +85C Junction Temperature Range. . . . . . . . . . . . . . . . . .-40C to +125C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 3. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER VCC SUPPLY CURRENT Nominal Supply POWER-ON RESET Rising VCC POR Threshold VCC POR Threshold Hysteresis OSCILLATOR Frequency
Recommended Operating Conditions, Unless Otherwise Noted. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
IVCC POR
2.6
3.2
3.8
mA
4.19 -
4.30 0.25
4.50 -
V V
fOSC DVOSC
ISL6520AC, VCC = 5V ISL6520AI, VCC = 5V
250 230 -
300 300 1.5
340 340 -
kHz kHz VP-P % % V
Ramp Amplitude REFERENCE Reference Voltage Tolerance
ISL6520AC ISL6520AI
-1.5 -2.5 -
0.800
+1.5 +2.5 -
Nominal Reference Voltage ERROR AMPLIFIER DC Gain Gain-Bandwidth Product Slew Rate GATE DRIVERS Upper Gate Source Current Upper Gate Sink Current Lower Gate Source Current Lower Gate Sink Current PROTECTION / DISABLE OCSET Current Source
VREF Guaranteed By Design GBWP SR
-
88 15 8
-
dB MHz V/s
IUGATE-SRC VBOOT - VPHASE = 5V, VUGATE = 4V IUGATE-SNK ILGATE-SRC VVCC = 5V, VLGATE = 4V ILGATE-SNK IOCSET VDISABLE ISL6520AC ISL6520AI
-
-1 1 -1 2
-
A A A A
17 14 -
20 20 0.8
22 24 -
A A V
Disable Threshold
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FN9016.5 March 28, 2007
ISL6520A Functional Pin Description
VCC
This pin provides the bias supply for the ISL6520A, as well as the lower MOSFET's gate. Connect a well-decoupled 5V supply to this pin. During soft-start, and all the time during normal converter operation, this pin represents the output of the error amplifier. Use this pin, in combination with the COMP/OCSET pin, to compensate the voltage-control feedback loop of the converter. Pulling COMP/OCSET to a level below 0.8V disables the controller. Disabling the ISL6520A causes the oscillator to stop, the LGATE and UGATE outputs to be held low, and the softstart circuitry to re-arm.
FB
This pin is the inverting input of the internal error amplifier. Use this pin, in combination with the COMP/OCSET pin, to compensate the voltage-control feedback loop of the converter.
LGATE
Connect this pin to the lower MOSFET's gate. This pin provides the PWM-controlled gate drive for the lower MOSFET. This pin is also monitored by the adaptive shootthrough protection circuitry to determine when the lower MOSFET has turned off.
GND
This pin represents the signal and power ground for the IC. Tie this pin to the ground island/plane through the lowest impedance connection available.
PHASE
Connect this pin to the upper MOSFET's source. This pin is used to monitor the voltage drop across the upper MOSFET for overcurrent protection.
Functional Description
Initialization
The ISL6520A automatically initializes upon receipt of power. The Power-On Reset (POR) function continually monitors the bias voltage at the VCC pin. The POR function initiates the Overcurrent Protection (OCP) sampling and hold operation after the supply voltage exceeds its POR threshold. Upon completion of the OCP sampling and hold operation, the POR function initiates the soft-start operation.
UGATE
Connect this pin to the upper MOSFET's gate. This pin provides the PWM-controlled gate drive for the upper MOSFET. This pin is also monitored by the adaptive shootthrough protection circuitry to determine when the upper MOSFET has turned off.
Overcurrent Protection
The overcurrent function protects the converter from a shorted output by using the upper MOSFET's on-resistance, rDS(ON), to monitor the current. This method enhances the converter's efficiency and reduces cost by eliminating a current sensing resistor. The overcurrent function cycles the soft-start function in a hiccup mode to provide fault protection. A resistor (ROCSET) programs the overcurrent trip level (see Typical Application diagram). Immediately following POR, the ISL6520A initiates the Overcurrent Protection sampling and hold operation. First, the internal error amplifier is disabled. This allows an internal 20mA current sink to develop a voltage across ROCSET. The ISL6520A then samples this voltage at the COMP pin. This sampled voltage, which is referenced to the VCC pin, is held internally as the Overcurrent Set Point. When the voltage across the upper MOSFET, which is also referenced to the VCC pin, exceeds the Overcurrent Set Point, the overcurrent function initiates a soft-start sequence. Figure 1 shows the inductor current after a fault is introduced while running at 15A. The continuous fault causes the ISL6520A to go into a hiccup mode with a typical period of 25ms. The inductor current increases to 18A during the softstart interval and causes an overcurrent trip. The converter dissipates very little power with this method. The measured input power for the conditions of Figure 1 is only 1.5W.
FN9016.5 March 28, 2007
BOOT
This pin provides ground referenced bias voltage to the upper MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive a logic-level N-channel MOSFET.
COMP/OCSET
This is a multiplexed pin. During a short period of time following power-on reset (POR), this pin is used to determine the overcurrent threshold of the converter. Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFET (VCC). ROCSET, an internal 20A current source (IOCSET), and the upper MOSFET on-resistance (rDS(ON)) set the converter overcurrent (OC) trip point according to the following equation:
I OCSET xR OCSET I PEAK = -----------------------------------------------r DS ( ON )
(EQ. 1)
Internal circuitry of the ISL6520A will not recognize a voltage drop across ROCSET larger than 0.5V. Any voltage drop across ROCSET that is greater than 0.5V will set the overcurrent trip point to:
0.5V I PEAK = ---------------------r DS ( ON )
(EQ. 2)
An overcurrent trip cycles the soft-start function.
5
ISL6520A
OUTPUT INDUCTOR CURRENT 5A/DIV.
VOUT 500mV/DIV. COMP/OCSET 1V/DIV.
TIME (5ms/DIV.)
TIME (2ms/DIV.)
FIGURE 1. OVERCURRENT OPERATION
FIGURE 2. SOFT-START INTERVAL
The overcurrent function will trip at a peak inductor current (IPEAK) determined by:
I OCSET x R OCSET I PEAK = ---------------------------------------------------r DS ( ON )
Current Sinking
The ISL6520A incorporates a MOSFET shoot-through protection method which allows a converter to sink current as well as source current. Care should be exercised when designing a converter with the ISL6520A when it is known that the converter may sink current. When the converter is sinking current, it is behaving as a boost converter that is regulating it's input voltage. This means that the converter is boosting current into the VCC rail, which supplies the bias voltage to the ISL6520A. If there is nowhere for this current to go, such as to other distributed loads on the VCC rail, through a voltage limiting protection device, or other methods, the capacitance on the VCC bus will absorb the current. This situation will allow voltage level of the VCC rail to increase. If the voltage level of the rail is boosted to a level that exceeds the maximum voltage rating of the ISL6520A, then the IC will experience an irreversible failure and the converter will no longer be operational. Ensuring that there is a path for the current to follow other than the capacitance on the rail will prevent this failure mode.
(EQ. 3)
where IOCSET is the internal OCSET current source (20A typical). The OC trip point varies mainly due to the MOSFET's rDS(ON) variations. To avoid overcurrent tripping in the normal operating load range, find the ROCSET resistor from the equation above with: 1. The maximum rDS(ON) at the highest junction temperature. 2. The minimum IOCSET from the specification table. 3. Determine IPEAK for I PEAK > I OUT ( MAX ) + ---------- , 2 where I is the output inductor ripple current. For an equation for the ripple current see the section under component guidelines titled `Output Inductor Selection'.
( I )
Soft-Start
The POR function initiates the soft-start sequence after the overcurrent set point has been sampled. Soft-start clamps the error amplifier output (COMP pin) and reference input (noninverting terminal of the error amp) to the internally generated soft-start voltage. Figure 2 shows a typical start up interval where the COMP/OCSET pin has been released from a grounded (system shutdown) state. Initially, the COMP/OCSET is used to sample the overcurrent setpoint by disabling the error amplifier and drawing 20A through ROCSET. Once the overcurrent level has been sampled, the soft-start function is initiated. The clamp on the error amplifier (COMP/OCSET pin) initially controls the converter's output voltage during soft-start. The oscillator's triangular waveform is compared to the ramping error amplifier voltage. This generates PHASE pulses of increasing width that charge the output capacitor(s). When the internally generated soft-start voltage exceeds the feedback (FB pin) voltage, the output voltage is in regulation. This method provides a rapid and controlled output voltage rise. The entire startup sequence typically take about 11ms.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible, using ground plane construction or single point grounding.
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FN9016.5 March 28, 2007
ISL6520A
VIN ISL6520A UGATE PHASE Q2
pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO).
LO OSC VOUT PWM COMPARATOR LOAD VOSC + DRIVER DRIVER VIN LO PHASE CO VOUT
Q1
LGATE
CIN
CO
RETURN
ZFB VE/A + ERROR AMP ZIN REFERENCE
ESR (PARASITIC)
FIGURE 3. PRINTED CIRCUIT BOARD POWER AND GROUND PLANES OR ISLANDS
Figure 3 shows the critical power components of the converter. To minimize the voltage overshoot, the interconnecting wires indicated by heavy lines should be part of a ground or power plane in a printed circuit board. The components shown in Figure 3 should be located as close together as possible. Please note that the capacitors CIN and CO may each represent numerous physical capacitors. Locate the ISL6520A within 3 inches of the MOSFETs, Q1 and Q2 . The circuit traces for the MOSFETs' gate and source connections from the ISL6520A must be sized to handle up to 1A peak current. Figure 4 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the COMP/OCSET pin and locate the resistor, ROSCET close to the COMP/OCSET pin because the internal current source is only 20A. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins. All components used for feedback compensation should be located as close to the IC a practical.
BOOT +5V CBOOT +VIN D1 Q1 LO VOUT LOAD
DETAILED COMPENSATION COMPONENTS C2 C1 R2 ZFB ZIN C3 R1 FB R3 VOUT
COMP + ISL6520A REFERENCE
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN
The modulator transfer function is the small-signal transfer function of VOUT/VE/A . This function is dominated by a DC Gain and the output filter (LO and CO), with a double pole break frequency at FLC and a zero at FESR . The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage VOSC .
Modulator Break Frequency Equations
1 F LC = -----------------------------------------2 x L O x C O 1 F ESR = ------------------------------------------2 x ESR x C O (EQ. 4)
ROCSET
ISL6520A
PHASE VCC +5V Q2 CVCC CO
COMP/OCSET
GND
FIGURE 4. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES
Feedback Compensation
Figure 5 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a 7
The compensation network consists of the error amplifier (internal to the ISL6520A) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees. The equations below relate the compensation network's poles, zeros and gain to the components (R1 , R2 , R3 , C1 , C2 , and C3) in Figure 7. Use these guidelines for locating the poles and zeros of the compensation network: 1. Pick Gain (R2/R1) for desired converter bandwidth. 2. Place 1ST Zero Below Filter's Double Pole (~75% FLC). 3. Place 2ND Zero at Filter's Double Pole. 4. Place 1ST Pole at the ESR Zero.
FN9016.5 March 28, 2007
ISL6520A
5. Place 2ND Pole at Half the Switching Frequency. 6. Check Gain against Error Amplifier's Open-Loop Gain. 7. Estimate Phase Margin - Repeat if Necessary. Modern components and loads are capable of producing transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor's ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the Equivalent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor's impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor.
Compensation Break Frequency Equations
1 F Z1 = ----------------------------------2 x R 2 x C 1 1 F Z2 = -----------------------------------------------------2 x ( R 1 + R 3 ) x C 3 1 F P1 = ------------------------------------------------------- C 1 x C 2 2 x R 2 x --------------------- C1 + C2 1 F P2 = ----------------------------------2 x R 3 x C 3 (EQ. 5)
Figure 6 shows an asymptotic plot of the DC/DC converter's gain vs frequency. The actual Modulator Gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 6. Using the above guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the graph of Figure 6 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin.
100 80 60 GAIN (dB) 40 20 0 -20 -40 -60 10 100 1K 20LOG (R2/R1) MODULATOR GAIN OPEN LOOP ERROR AMP GAIN
Output Inductor Selection
The output inductor is selected to meet the output voltage ripple requirements and minimize the converter's response time to the load transient. The inductor value determines the converter's ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations:
I = VIN - VOUT Fs x L x VOUT VIN VOUT = I x ESR
FZ1 FZ2
FP1
FP2
20LOG (VIN/DVOSC) COMPENSATION GAIN FLC 10K CLOSED LOOP GAIN FESR 100K 1M 10M
(EQ. 6)
Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter's response time to a load transient. One of the parameters limiting the converter's response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL6520A will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following
FN9016.5 March 28, 2007
FREQUENCY (Hz)
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. 8
ISL6520A
equations give the approximate response time interval for application and removal of a transient load:
tRISE = L x ITRAN VIN - VOUT tFALL = L x ITRAN VOUT (EQ. 7)
where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. The worst case response time can be either at the application or removal of load. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time.
equations below). These equations assume linear voltagecurrent transitions and do not adequately model power loss due the reverse-recovery of the upper and lower MOSFET's body diode. The gate-charge losses are dissipated by the ISL6520A and don't heat the MOSFETs. However, large gatecharge increases the switching interval, tSW which increases the MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. Losses while Sourcing Current
2 1 P UPPER = Io x r DS ( ON ) x D + -- Io x V IN x t SW x F S 2
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time Q1 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the source of Q2 . The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current. For a through hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge currentrating. These capacitors must be capable of handling the surge-current at power-up. Some capacitor series available from reputable manufacturers are surge current tested.
PLOWER = Io2 x rDS(ON) x (1 - D)
Losses while Sinking Current
PUPPER = Io2 x rDS(ON) x D
2 1 P LOWER = Io x r DS ( ON ) x ( 1 - D ) + -- Io x V IN x t SW x F S 2
Where: D is the duty cycle = VOUT / VIN , tSW is the combined switch ON and OFF time, and (EQ. 8) FS is the switching frequency.
Given the reduced available gate bias voltage (5V), logic-level or sub-logic-level transistors should be used for both N-MOSFETs. Caution should be exercised with devices exhibiting very low VGS(ON) characteristics. The shootthrough protection present aboard the ISL6520A may be circumvented by these MOSFETs if they have large parasitic impedences and/or capacitances that would inhibit the gate of the MOSFET from being discharged below it's threshold level before the complementary MOSFET is turned on.
+5V DBOOT + VD BOOT +5V
VCC
MOSFET Selection/Considerations
The ISL6520A requires 2 N-Channel power MOSFETs. These should be selected based upon rDS(ON) , gate supply requirements, and thermal management requirements. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the upper and the lower MOSFETs. These losses are distributed between the two MOSFETs according to duty factor. The switching losses seen when sourcing current will be different from the switching losses seen when sinking current. When sourcing current, the upper MOSFET realizes most of the switching losses. The lower switch realizes most of the switching losses when the converter is sinking current (see the
+
ISL6520A
UGATE PHASE
CBOOT Q1 NOTE: VG-S VCC -VD Q2 NOTE: VG-S VCC GND
-
LGATE
FIGURE 7. UPPER GATE DRIVE BOOTSTRAP
Figure 7 shows the upper gate drive (BOOT pin) supplied by a bootstrap circuit from VCC . The boot capacitor, CBOOT, develops a floating supply voltage referenced to the PHASE pin. The supply is refreshed to a voltage of VCC less the boot diode drop (VD) each time the lower MOSFET, Q2 , turns on.
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ISL6520A ISL6520A DC/DC Converter Application Circuit
Figure 8 shows an application circuit of a DC/DC Converter. Detailed information on the circuit, including a complete Bill-of-Materials and circuit board description, can be found in Application Note AN9932.
+5V 0.1F + CIN 2 x 330F VCC 6.19k ISL6520A 5 1 BOOT D1 2 x 1F
MONITOR AND PROTECTION COMP/OCSET 7 REF 10.0k 470pF 8200pF FB 6 OSC 1.00k U1 3 GND 3.16k + + -
2 UGATE 8 PHASE Q1
0.1F L1 VOUT
4
LGATE Q2 + COUT 3 x 330F 0.1F
60.4
18000pF
Component Selection Notes: CIN - Each 330mF 6.3WVDC, Sanyo 6TPB330M or Equivalent. COUT - Each 330mF 6.3WVDC, Sanyo 6TPB330M or Equivalent. D1 - 30mA Schottky Diode, MA732 or Equivalent L1 - 3.1H Inductor, Panasonic P/N ETQ-P6F2ROLFA or Equivalent. Q1 , Q2 - Intersil MOSFET; HUF76143.
FIGURE 8. 5V to 3.3V 15A DC/DC CONVERTER
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ISL6520A Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45 H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 8 8 0 8 MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 0.2284 0.0099 0.016 8 0
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 0.2440 0.0196 0.050
B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC
1.27 BSC
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
11
FN9016.5 March 28, 2007
ISL6520A Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220-VGGC ISSUE C) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.50 1.95 1.95 0.23 MIN 0.80 NOMINAL 0.90 0.20 REF 0.28 4.00 BSC 3.75 BSC 2.10 4.00 BSC 3.75 BSC 2.10 0.65 BSC 0.60 16 4 4 0.60 12 0.75 0.15 2.25 2.25 0.35 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 5 5/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN9016.5 March 28, 2007

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